Multi-level integrated circuit (IC) manufacturing requires many steps of metal and insulator film depositions followed by photoresist patterning and etching or other means of material removal. After photolithography and etching, the resulting wafer or substrate surface is non-planar and contains many features such as vias, lines, or channels. Often, these features need to be filled with a specific material such as a metal, a dielectric, or both. For high performance applications, the wafer topographic surface needs to be planarized, making it ready again for the next level of processing, which commonly involves deposition of a material and a photolithographic step. It is most preferred that the substrate surface be flat for proper focusing and level for level registration or alignment. Therefore, after each deposition step that yields a non-planar surface on the wafer, there is often a step of surface planarization or polishing.
Electrodeposition is a widely accepted technique used in IC manufacturing for the deposition of a highly conductive material such as copper into features such as vias and channels in an insulating layer on the semiconductor wafer surface. FIGS. 1a through 1c show an example of the procedure for filling surface features with electrodeposited copper and then polishing the wafer to obtain a structure with a planar surface and electrically isolated Cu plugs or wires.
Features in FIG. 1a are opened in the insulator layer 2 and are to be filled with Cu. To achieve this, a barrier layer 3 is first deposited over the whole wafer surface. Then, a conductive Cu seed layer 4 is deposited over the barrier layer 3. Upon making electrical contact with the Cu seed layer 4, and applying electrical power, Cu is electrodeposited over the wafer surface to obtain the structure depicted in FIG. 1b. As can be seen in FIG. 1b, in this conventional approach, the electrodeposited Cu layer 5 forms a metal overburden 6 on the barrier layer disposed on the top surface of the insulator layer 2. This overburden and portions of the barrier layer 3 are then removed by polishing, yielding the structure shown in FIG. 1c which has a planar surface and electrically isolated Cu-filled features.
Electrodeposition is commonly carried out cathodically in a specially formulated electrolyte containing copper ions as well as additives that control the texture, morphology, and plating behavior of the copper layer. A proper electrical contact is made to the seed layer on the wafer surface, typically along the circumference of the round wafer. A consumable Cu or inert anode plate is placed in the electrolyte. Deposition of Cu on the wafer surface can then be initiated when a cathodic potential is applied to the wafer surface with respect to the anode, i.e., when a negative voltage is applied to the wafer surface with respect to the anode plate.
For a wafer holder that is used to electrodeposit a conductive material such as copper onto the surface of a wafer, it is important that the electrical contact be made properly with the conductive seed layer. This contact should be protected from the electroplating solution to avoid deposition of material onto the contact itself and to avoid corrosion of the contact by the electrolyte chemicals. The backside of the wafer should also be protected against the electrolyte.
Chemical Mechanical Polishing (CMP) is a widely used method of surface planarization. In CMP, the wafer is loaded on a carrier head, and a wafer surface with non-planar features is brought into contact with a polishing pad and an appropriately selected polishing slurry. Abrasive particles that may range from 100 microns to submicronic in size are contained in the pad, the polishing slurry, or both the pad and the polishing slurry. The pad and the wafer are then pressed together and moved with respect to each other to initiate polishing and eventually yield the desired planar surface. The chemistry of the polishing slurry and the type of the abrasive particles used are selected according to the chemical nature of the material to be polished. Therefore, the chemical compositions of polishing slurries for copper, tungsten, tantalum, tantalum nitride, silicon dioxide, and like materials used in IC manufacturing may all be different.
The part of a typical CMP machine that holds the workpiece, the substrate, or the wafer in place during the polishing operation is called the carrier head. Various designs for CMP carrier heads have been described in various patents. Each of these designs addresses a specific issue that is important in CMP. For example, U.S. Pat. No. 5,795,215 discloses a retaining ring design to pre-compress a polishing pad to reduce an edge effect during polishing. U.S. Pat. No. 5,681,215 describes the use of multiple bellows to properly transfer torque to a carrier base while allowing the carrier base to pivot. U.S. Pat. No. 5,762,544 relates to a specific gimbal mechanism that allows a carrier base, and thus the wafer surface, to pivot about a point at the interface between the wafer and a polishing pad. Without going into specific pecularities of various designs, it can generally be stated that a typical carrier head used in a CMP operation needs to:
a) restrain the wafer in place under the head during the polishing process;
b) provide mechanical strength and stability as well as a uniform pressure across the wafer when the wafer is pushed against the polishing pad; and
c) keep all portions of the wafer surface substantially parallel to the pad surface to achieve local as well as global planarity.
The customary approach to achieve the metal deposition and polishing steps depicted in FIGS. 1b and 1c is to use two different processes in two different machines; one process in a first machine is used for deposition of a conductor such as copper, and a second process in a second machine is used for chemical mechanical polishing to obtain planarization. Copending U.S. patent application Ser. No. 09/201,929, filed on Dec. 1, 1998 and titled xe2x80x9cMethod and Apparatus for Electrochemical Mechanical Depositionxe2x80x9d, relates to a method and apparatus to achieve both deposition and polishing steps in the same apparatus at the same time or in a sequential manner. This application describes a carrier head design that can be used in a CMP machine as well as in an electroplating machine. Our preferred use of this design, however, is in a machine that does both plating and polishing.
It is a primary object of the present invention to provide an improved carrier head configuration which can be used in both plating and polishing operations. According to the present invention, the carrier head is self loading. An operator or a robot feeds a wafer onto an open clamp ring. The clamp ring then closes, placing the wafer onto a chuck face and securing it in place so that the wafer is ready for the plating and polishing procedures. Unloading is similarly easy. Loading and unloading can be done from both sides of the head.
Capabilities have been built into the head design to permit i) rotation of the substrate at controlled speeds in both clockwise and counter-clockwise directions, ii) pushing of the wafer surface against the pad surface at controlled pressures during rotation, iii) provision of gimble action to the wafer so as to ensure uniform pressure distribution across the wafer surface, iv) electrical contact with the wafer surface all around its perimeter, v) protection of the electrical contact from the corrosive electrolyte through a novel seal design, vi) protection of the back side of the wafer from contacting the electrolyte, and vii) provision of a backing pad, on which the wafer rests, which has unique surface features to increase friction with the back side of the wafer and to aid in wafer loading and unloading procedures.
According to the invention, a work piece carrier head can carry a semiconductor wafer during both plating and polishing operations. The carrier head includes a first component secured to a shaft by which the carrier head can be rotated, translated, and moved up and down, a second component connected to the first component and movable relative to the first component between retracted and extended positions, and a third component connected to the first and second components for up and down movement between wafer loading or unloading and wafer plating or polishing positions.
The third component is biased away from the wafer loading or unloading position and towards the wafer plating or polishing position to self-load the wafer to the carrier head. The first and second components define an expandable volume therebetween. Fluid can be supplied to or discharged from the expandable volume to produce relative movement of the first and second components. This relative movement is used to control a distance between a surface of the wafer and a source of plating material during the plating operation, and to control pressure at an interface between the surface of the wafer and a polishing pad surface during the polishing operation.
Stops are defined on the first component which limit movement of the second component and define respective fully retracted and fully extended positions of the second component. A gimbal mechanism is rendered effective when the second component is released from the stops to assure uniform pressure across the wafer during polishing.
The third component includes a contact element by which an electrical contact with the wafer is provided to permit wafer plating. The contact element may be formed by a contact ring, or may be formed by several conductive pieces which form a contact ring. The contact element is sandwiched between sections of the third component, and includes a seal mounted between the contact element and one of these sections. The seal isolates the electrical contact from electrolyte during the plating operation.
The second component includes holes extending through a face thereof by which the wafer can be pulled under vacuum towards and blown under pressure away from the face. A soft backing pad is mounted on the face of the second component and has a rough or textured surface facing the wafer during the plating and polishing operations.